FIG. 1 demonstrates a basic methodology that is often employed when a semiconductor manufacturing process (which may also be referred to as a “process” or a “semiconductor process”) is evaluated. A semiconductor manufacturing process is usually evaluated in order to understand whether or not a particular circuit design can be fabricated with the process in question; or, what functional characteristics or limits might apply if a particular circuit design is fabricated by the process in question. According to the methodology of FIG. 1, device models that describe characteristics of the various types of devices (e.g., transistors) manufactured by the process in question are provided to a designer (e.g., what drain-to-source current can be expected for a particular gate-to-source voltage and drain-to-source voltage); who, through considerable manual efforts, designs 101 a circuit with the device models.
That is, specific features of the design are articulated only as a result of conscious decision making on the part of the designer based upon his/her design objectives; and, his/her knowledge of the device model particulars. For example, the gate width of a particular transistor may be manually determined in light of a drain-to-source current that is desired by the designer for the transistor; and, a transconductance-per-unit-gate-width parameter for the transistor that is defined (or can be derived from) the device model for the transistor. As such, the present day design approach 101 often involves the designer having to consciously make trade-offs between his/her design goals and the capabilities of the process.
During the design phase 101 a design is usually formulated through the construction of a “netlist”. A netlist is a data format that lists the nodes in the design's circuitry network and the device components connected thereto (e.g., a transistor's gate, a transistor's source, a first capacitor electrode, etc.). Device features are also usually specified (such as the width of a transistor's gate, etc.) In order to verify that a design's operation conforms to specific functional requirements (or to observe the effects of a design “experiment”), a design's operation can be simulated 102 with a software tool that uses the netlist as basis for performing the simulation. The simulation results may include waveforms that are expected to appear on a particular node as well as frequency response characteristics.
A problem with the traditional design flow is that it is heavily dependent on the designer's manual efforts which can consume long periods of time. As a consequence, evaluating a number of different potential manufacturing processes for a particular design is inefficient because an attempt has to be made at developing a working design for each process to be evaluated. Given the manual efforts associated with each design 101 attempt, the number of potential processes that are entertained for a particular design (and/or the number of process that can be evaluated) are often limited to a select few.